The present invention relates generally to improved semiconductor imaging devices and in particular to a silicon imaging device having a multi-layered gate and a second gate which overlaps the multi-layered gate, and that can be fabricated using a standard CMOS process.
There are a number of different types of semiconductor-based imagers, including charge coupled devices (CCDs), photodiode arrays, charge injection devices and hybrid focal plane arrays. CCD technology is often employed for image acquisition and enjoys a number of advantages which makes it the incumbent technology, particularly for small size imaging applications. CCDs are capable of large formats with small pixel size and they employ low noise charge domain processing techniques.
However, CCD imagers also suffer from a number of disadvantages. For example, they are susceptible to radiation damage, they exhibit destructive read-out over time, they require good light shielding to avoid image smear and they have a high power dissipation for large arrays. Additionally, while offering high performance, CCD arrays are difficult to integrate with CMOS processing in part due to a different processing technology and to their high capacitances, complicating the integration of on-chip drive and signal processing electronics with the CCD array. While there have been some attempts to integrate on-chip signal processing with CCD arrays, these attempts have not been entirely successful. CCDs also must transfer an image by line charge transfers from pixel to pixel, requiring that the entire array be read out into a memory before individual pixels or groups of pixels can be accessed and processed. This takes time. CCDs may also suffer from incomplete charge transfer from pixel to pixel which results in image smear.
Because of the inherent limitations in CCD technology, there is an interest in CMOS imagers for possible use as low cost imaging devices. A filly compatible CMOS sensor technology enabling a higher level of integration of an image array with associated processing circuits would be beneficial to many digital applications such as, for example, in cameras, scanners, machine vision systems, vehicle navigation systems, video telephones, computer input devices, surveillance systems, auto focus systems, star trackers, motion detection systems, image stabilization systems and data compression systems for high-definition television.
The advantages of CMOS imagers over CCD imagers are that CMOS imagers have a low voltage operation and low power consumption; CMOS imagers are compatible with integrated on-chip electronics (control logic and timing, image processing, and signal conditioning such as A/D conversion); CMOS imagers allow random access to the image data; and CMOS imagers have lower fabrication costs as compared with the conventional CCD because standard CMOS processing techniques can be used. Additionally, low power consumption is achieved for CMOS imagers because only one row of pixels at a time needs to be active during the readout and there is no charge transfer (and associated switching) from pixel to pixel during image acquisition. On-chip integration of electronics is particularly advantageous because of the potential to perform many signal conditioning functions in the digital domain (versus analog signal processing) as well as to achieve a reduction in system size and cost.
A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including either a photogate, photoconductor or a photodiode overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. A readout circuit is connected to each pixel cell and includes at least an output field effect transistor formed in the substrate and a charge transfer section formed on the substrate adjacent the photogate, photoconductor or photodiode having a sensing node, typically a floating diffusion node, connected to the gate of an output transistor. The imager may include at least one electronic device such as a transistor for transferring charge from the underlying portion of the substrate to the floating diffusion node and one device, also typically a transistor, for resetting the node to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to the floating diffusion node accompanied by charge amplification; (4) resetting the floating diffusion node to a known state before the transfer of charge to it; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the floating diffusion node. The charge at the floating diffusion node is typically converted to a pixel output voltage by a source follower output transistor. The photosensitive element of a CMOS imager pixel is typically either a depleted p-n junction photodiode or a field induced depletion region beneath a photogate or photoconductor. For photodiodes, image lag can be eliminated by completely depleting the photodiode upon readout.
CMOS imagers of the type discussed above are generally known as discussed, for example, in Nixon et al., xe2x80x9c256xc3x97256 CMOS Active Pixel Sensor Camera-on-a-Chip,xe2x80x9d IEEE Journal of Solid-State Circuits, Vol. 31(12), pp. 2046-2050 (1996); Mendis et al., xe2x80x9cCMOS Active Pixel Image Sensors,xe2x80x9d IEEE Transactions on Electron Devices, Vol. 41(3), pp. 452-453 (1994), as well as U.S. Pat. No. 5,708,263 and U.S. Pat. No. 5,471,515, which are herein incorporated by reference.
To provide context for the invention, an exemplary CMOS imaging circuit is described below with reference to FIG. 1. The circuit described below, for example, includes a photogate for accumulating photo-generated charge in an underlying portion of the substrate. It should be understood that the CMOS imager may include a photodiode or other image to charge converting device, in lieu of a photogate, as the initial accumulator for photo-generated charge.
Reference is now made to FIG. 1 which shows a simplified circuit for a pixel of an exemplary CMOS imager using a photogate and having a pixel photodetector circuit 14 and a readout circuit 60. It should be understood that while FIG. 1 shows the circuitry for operation of a single pixel, that in practical use there will be an Mxc3x97N array of pixels arranged in rows and columns with the pixels of the array accessed using row and column select circuitry, as described in more detail below.
The photodetector circuit 14 is shown in part as a cross-sectional view of a semiconductor substrate 16 typically a p-type silicon, having a surface well of p-type material 20. An optional layer 18 of p-type material may be used if desired, but is not required. Substrate 16 may be formed of, for example, Si, SiGe, Ge, or GaAs. Typically the entire substrate 16 is p-type doped silicon substrate and may contain a surface p-well 20 (with layer 18 omitted), but many other options are possible, such as, for example p on pxe2x88x92 substrates, p on p+ substrates, p-wells in n-type substrates or the like. The terms wafer or substrate used in the description includes any semiconductor-based structure having an exposed surface in which to form the circuit structure used in the invention. Wafer and substrate are to be understood as including silicon-on-insulator (SOI) technology, silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure or foundation.
An insulating layer 22 such as, for example, silicon dioxide is formed on the upper surface of p-well 20. The p-type layer may be a p-well formed in substrate 16. A photogate 24 thin enough to pass radiant energy or of a material which passes radiant energy is formed on the insulating layer 22. The photogate 24 receives an applied control signal PG which causes the initial accumulation of pixel charges in n+ region 26. The n+ type region 26, adjacent one side of photogate 24, is formed in the upper surface of p-well 20. A transfer gate 28 is formed on insulating layer 22 between n+ type region 26 and a second n+ type region 30 formed in p-well 20. The n+ regions 26 and 30 and transfer gate 28 form a charge transfer transistor 29 which is controlled by a transfer signal TX. The n+ region 30 is typically called a floating diffusion region. It is also a node for passing charge accumulated thereat to the gate of a source follower transistor 36 described below.
A reset gate 32 is also formed on insulating layer 22 adjacent and between n+ type region 30 and another n+ region 34 which is also formed in p-well 20. The reset gate 32 and n+ regions 30 and 34 form a reset transistor 31 which is controlled by a reset signal RST. The n+ type region 34 is coupled to voltage source VDD, e.g., 5 volts. The transfer and reset transistors 29, 31 are n-channel transistors as described in this implementation of a CMOS imager circuit in a p-well. It should be understood that it is possible to implement a CMOS imager in an n-well in which case each of the transistors would be p-channel transistors. It should also be noted that while FIG. 1 shows the use of a transfer gate 28 and associated transistor 29, this structure provides advantages, but is not required.
Photodetector circuit 14 also includes two additional n-channel transistors, source follower transistor 36 and row select transistor 38. Transistors 36, 38 are coupled in series, source to drain, with the source of transistor 36 also coupled over lead 40 to voltage source VDD and the drain of transistor 38 coupled to a lead 42. The drain of row select transistor 38 is connected via conductor 42 to the drains of similar row select transistors for other pixels in a given pixel row. A load transistor 39 is also coupled between the drain of transistor 38 and a voltage source VSS, e.g. 0 volts. Transistor 39 is kept on by a signal VLN applied to its gate.
The imager includes a readout circuit 60 which includes a signal sample and hold (S/H) circuit including a S/H n-channel field effect transistor 62 and a signal storage capacitor 64 connected to the source follower transistor 36 through row transistor 38. The other side of the capacitor 64 is connected to a source voltage VSS. The upper side of the capacitor 64 is also connected to the gate of a p-channel output transistor 66. The drain of the output transistor 66 is connected through a column select transistor 68 to a signal sample output node VOUTS and through a load transistor 70 to the voltage supply VDD. A signal called xe2x80x9csignal sample and holdxe2x80x9d (SHS) briefly turns on the S/H transistor 62 after the charge accumulated beneath the photogate electrode 24 has been transferred to the floating diffusion node 30 and from there to the source follower transistor 36 and through row select transistor 38 to line 42, so that the capacitor 64 stores a voltage representing the amount of charge previously accumulated beneath the photogate electrode 24.
The readout circuit 60 also includes a reset sample and hold (S/H) circuit including a S/H transistor 72 and a signal storage capacitor 74 connected through the S/H transistor 72 and through the row select transistor 38 to the source of the source follower transistor 36. The other side of the capacitor 74 is connected to the source voltage VSS. The upper side of the capacitor 74 is also connected to the gate of a p-channel output transistor 76. The drain of the output transistor 76 is connected through a p-channel column select transistor 78 to a reset sample output node VOUTR and through a load transistor 80 to the supply voltage VDD. A signal called xe2x80x9creset sample and holdxe2x80x9d (SHR) briefly turns on the S/H transistor 72 immediately after the reset signal RST has caused reset transistor 31 to turn on and reset the potential of the floating diffusion node 30, so that the capacitor 74 stores the voltage to which the floating diffusion node 30 has been reset.
The readout circuit 60 provides correlated sampling of the potential of the floating diffusion node 30, first of the reset charge applied to node 30 by reset transistor 31 and then of the stored charge from the photogate 24. The two samplings of the diffusion node 30 charges produce respective output voltages VOUTR and VOUTS of the readout circuit 60. These voltages are then subtracted (VOUTSxe2x88x92VOUTR) by subtractor 82 to provide an output signal terminal 81 which is an image signal independent of pixel to pixel variations caused by fabrication variations in the reset voltage transistor 31 which might cause pixel to pixel variations in the output signal.
FIG. 2 illustrates a block diagram for a CMOS imager having a pixel array 200 with each pixel cell being constructed in the manner shown by element 14 of FIG. 1. FIG. 4 shows a 2xc3x972 portion of pixel array 200. Pixel array 200 comprises a plurality of pixels arranged in a predetermined number of columns and rows. The pixels of each row in array 200 are all turned on at the same time by a row select line, e.g., line 86, and the pixels of each column are selectively output by a column select line, e.g., line 42. A plurality of rows and column lines are provided for the entire array 200. The row lines are selectively activated by the row driver 210 in response to row address decoder 220 and the column select lines are selectively activated by the column driver 260 in response to column address decoder 270. Thus, a row and column address is provided for each pixel. The CMOS imager is operated by the control circuit 250 which controls address decoders 220, 270 for selecting the appropriate row and column lines for pixel readout, and row and column driver circuitry 210, 260 which apply driving voltage to the drive transistors of the selected row and column lines.
FIG. 3 shows a simplified timing diagram for the signals used to transfer charge out of photodetector circuit 14 of the FIG. 1 CMOS imager. The photogate signal PG is nominally set to 5V and pulsed from 5V to 0V during integration. The reset signal RST is nominally set at 2.5V. As can be seen from the figure, the process is begun at time t0 by briefly pulsing reset voltage RST to 5V. The RST voltage, which is applied to the gate 32 of reset transistor 31, causes transistor 31 to turn on and the floating diffusion node 30 to charge to the VDD voltage present at n+ region 34 (less the voltage drop VTH of transistor 31). This resets the floating diffusion node 30 to a predetermined voltage (VDDxe2x88x92VTH). The charge on floating diffusion node 30 is applied to the gate of the source follower transistor 36 to control the current passing through transistor 38, which has been turned on by a row select (ROW) signal, and load transistor 39. This current is translated into a voltage on line 42 which is next sampled by providing a SHR signal to the S/H transistor 72 which charges capacitor 74 with the source follower transistor output voltage on line 42 representing the reset charge present at floating diffusion node 30. The PG signal is next pulsed to 0 volts, causing charge to be collected in n+ region 26.
A transfer gate voltage TX, similar to the reset pulse RST, is then applied to transfer gate 28 of transistor 29 to cause the charge in n+ region 26 to transfer to floating diffusion node 30. It should be understood that for the case of a photogate, the transfer gate voltage TX may be pulsed or held to a fixed DC potential. For the implementation of a photodiode with a transfer gate, the transfer gate voltage TX must be pulsed. The new output voltage on line 42 generated by source follower transistor 36 current is then sampled onto capacitor 64 by enabling the sample and hold switch 62 by signal SHS. The column select signal is next applied to transistors 68 and 70 and the respective charges stored in capacitors 64 and 74 are subtracted in subtractor 82 to provide a pixel output signal at terminal 81. It should also be noted that CMOS imagers may dispense with the transfer gate 28 and associated transistor 29, or retain these structures while biasing the transfer transistor 29 to an always xe2x80x9conxe2x80x9d state.
The operation of the charge collection of the CMOS imager is known in the art and is described in several publications such as Mendis et al., xe2x80x9cProgress in CMOS Active Pixel Image Sensors,xe2x80x9d SPIE Vol. 2172, pp. 19-29 (1994); Mendis et al., xe2x80x9cCMOS Active Pixel Image Sensors for Highly Integrated Imaging Systems,xe2x80x9d IEEE Journal of Solid State Circuits, Vol. 32(2) (1997); and Eric R Fossum, xe2x80x9cCMOS Image Sensors: Electronic Camera on a Chip,xe2x80x9d IEDM Vol. 95, pp. 17-25 (1995) as well as other publications. These references are incorporated herein by reference.
The pixel cell 14 shown in FIG. 1 contains a transfer transistor 29 having a gate stack 28, a source n+ region 26 and a drain floating diffusion region 30. Because the transfer gate stack 28 is separated from the photogate 24 by a relatively wide gap, e.g., 0.25 microns, the presence of a coupling region 26 is necessary to electrically couple the photogate 24 to the transfer gate stack 28. When a signal TX is applied to the transfer gate stack 28, the coupling region 26 functions as a conducting channel to pass charges from the doped layer 27 under the photogate into the channel region of the transfer transistor 29, and then to the floating diffusion region 30. Although this pixel cell 14 is simple to fabricate because it is a single polysilicon process, i.e., it uses a single layer of polysilicon as the gate layer in the photogate 24, transfer gate 28 and reset gate 32, it has the disadvantages of added noise and incomplete charge transfer as a result of having to incorporate the diffused region 26.
To overcome these disadvantages, double polysilicon structures have been developed in which the photogate 24 and reset gate 32 are formed using the same layer of polysilicon. After spacer formation the top surface of all polysilicon gates are then oxidized, and then a transfer gate 28 is formed from a second layer of polysilicon that overlaps the photogate 24 to some degree. The overlapping of the photogate 24 and the transfer gate 28 with only a thin, e.g., less than 100 nm, layer of spacer insulator between them permits electrical coupling to occur between the doped layer 27 underlying the photogate 24 and the floating diffusion region 30. No coupling region 26 is required for this pixel cell 14. Although this pixel cell 14 provides improved control over the potential stored in the 100 nm overlapping region between the edge of the photogate 24 and the transfer gate 28, and results in increased charge transfer from the doped layer 27 to the floating diffusion region 30, there are significant processing difficulties in the fabrication methods used to create the pixel cell 14. The oxidation of the photogate stack 24 prior to transfer gate stack 28 formation results in asperities, points, and other defects in the oxide layer insulating the transfer gate polysilicon from the photogate polysilicon, resulting in low breakdown of the insulating gate oxide between these two overlying polysilicons, improper electrical functioning, and poor processing yield. Additionally, this oxidation of the first polysilicon layer, prior to the deposition of the second polysilicon layer which will form the transfer gate 28, forms the second gate oxide under the transfer gate. As geometries have shrunk to improve performance and yield, the gate oxide must be grown thinner to maintain low threshold voltages and maintain performance at the shorter geometries. So the thinning of the second gate oxide continues to cause a degradation in the breakdown voltage between these two overlapping polysilicon layers.
This process also suffers from the alignment required to do the masked implant of the n-doped region 27, requiring careful alignment so that the doped region 27 does not extend across the transfer gate 28 which will be formed in later processing. In order to achieve this the transfer gate 28 is made larger to account for implant misalignment errors. This process also suffers from the fact that all transistors formed by the first polysilicon deposition including the photogate 24 and reset gate 32 cannot be silicided gates, which would improve circuit speed and performance, because of two reasons: (1) the top silicide cannot be oxidized to provide a reliable insulating oxide between the photogate 24 and the transfer gate 28 and (2) a silicide layer on top of the photogate would block signal light from passing through the photogate into the signal storage region 27 below the photogate.
There is needed, therefore, an improved multi-layered gate structure formed with an overlapping second gate so that a doped region is not required to transfer charge between the two gates. Also needed is a multi-layered transfer gate 28 and an overlapping photogate 24, or a multi-layered photogate 24 with an overlapping transfer gate 28 so that a n-doped region 26 is not required. A method of fabricating a multi-layered gate that solves the reduced process yield associated with the low photogate polysilicon to transfer polysilicon breakdown voltage is needed. It would also be advantageous if this new method would also provide silicided gates for improved speed and circuit performance while simultaneously allowing signal light to pass through the photogate.
The present invention provides a multi-layered gate stack process for use in fabricating a pixel sensor cell. The multi-layered gates have multiple layers including a conductive layer, an optional silicide layer, and an insulating layer, all of which are patterned and etched simultaneously over a first insulating layer. Also provided are methods for forming the multi-layered gates of the present invention, and a process that achieves high yield overlap process for a photogate-transfer gate overlap that does not require the n-doped region 26. The combination of a multi-layered gate and an overlapping gate may be a multi-layered transfer gate with an overlapping photogate, a multi-layered photogate with an overlapping transfer gate, a multi-layered source follower gate with an overlapping row select gate, a multi-layered row select gate with an overlapping source follower gate, or any other suitable combination.
Additional advantages and features of the present invention will be apparent from the following detailed description and drawings which illustrate preferred embodiments of the invention.